********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 14, 2014
*ECN S14-0759, Rev. B
*File Name: Si7456DDP_PS.txt and Si7456DDP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7456DDP D G S 
M1 3 GX S S NMOS W= 1429559u L= 0.25u 
M2 S GX S D PMOS W= 1429559u L= 0.49u 
R1 D 3 1.435e-02 TC=6.174e-03, 1.724e-05 
CGS GX S 6.681e-10 
CGD GX D 1.000e-13 
RG G GY 0.85
RTCV 100 S 1e6 TC=1.598e-05, 1.160e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 1429559u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 9.189e-06 NSUB = 1.29e+17 
+ KAPPA = 2.894e-02 NFS = 4.000e+11 
+ LD = 0 IS = 0 TPG = 1   ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.585e+16 IS = 0 TPG = -1  ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 7.977e-08 T_MEASURED = 25 BV = 101 
+RS = 5.174e-03 N = 1.074e+00 IS = 3.997e-12 
+EG = 1.114e+00 XTI = -1.218e-01 TRS1 = 6.630e-04 
+CJO = 5.587e-10 VJ = 2.000e+01 M = 8.027e-01 ) 
.ENDS 
